Mr. Jagannath Samanta
Designation : Assistant Professor
Phone No. : 03224-252900 Extn:302
Email : jagannath19060@gmail.com
Contact Details :
Faculty Room-4, Department of Electronics & Communication Engineering, Haldia Institute of Technology, ICARE Complex, Hatiberia, Haldia, West Bengal, 721657
Odd Semester 2015-16 |
Microelectronics & VLSI Designs (EC-702) |
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VLSI Design Lab (EC-792) |
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Digital IC Design (MVLSI-103) |
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CAD Tools for VLSI Design (MVLSI-191) |
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Even Semester 2015-16 |
Information Theory & Coding (EC-604B) |
Course Home |
Physical Design & Testing (MVLSI-204D) |
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Basic Electrical and Electronics engg.-II (ES-201) |
Course Home |
Digital VLSI Design, Error Correcting Codes
[1] | B P De and J. Samanta, “Thermal bound placement with wire length consideration for standard cells in VLSI”, IJCSI International Journal of Computer Science Issues, Special Issue, ICVCI-2011, Vol. 1, Issue 1, pp:19-22, ISSN (Online): 1694-0814, November 2011. |
[2] | J. Samanta, B. P. De, B. Bag & R. K. Maity, “Comparative study for delay & power dissipation of CMOS Inverter in UDSM range”, International Journal of Soft Computing and Engineering (IJSCE), ISSN: 2231-2307,Volume-1, Issue-6, pp:162-167,January2012. |
[3] | R. K. Maity, J. Samanta, “Construction and performance studies of a pseudo-orthogonal code for fiber optic CDMA LAN”, International Journal of Soft Computing and Engineering (IJSCE), ISSN: 2231-2307, Volume-1, Issue-6, pp: 196-201, January 2012. |
[4] | J. Samanta, A Patra, D Mishra, R Rashmi, I Kundu & R Koley, “Performance Analysis of Different Topologies of 1-Bit Full Adder in UDSM Technology”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-1, Issue-2, pp:35-42, July-2012. |
[5] | J. Samanta, M. Halder, B. P. De, “Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles” International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, pp:330-336, Jan- 2013. |
[6] | Bhaumik, A. S. Das and J. Samanta, “Architecture for Programmable Generator Polynomial Based Reed-Solomon Encoder and Decoder” International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, pp:395-399, Jan- 2013. |
[7] | R. Sultana and J. Samanta, “Comparison of different design techniques of XOR & AND gate using EDA simulation tool”, International Journal of VLSI and Embedded Systems (IJVES), ISSN: 2249–6556, Vol-04, Issue-03, pp:343-349, May - June 2013 |
[8] | M. Basak, M. Sutradhar, B. Santra, M. Saha, D. Chowdhury and J. Samanta, “Study the performance analysis of low power –high speed carry select adder using EDA simulation tool”, International Journal of VLSI and Embedded Systems (IJVES), ISSN: 2249–6556, Vol-04, Article-06102, pp:444-448, June 2013. |
[9] | J. Samanta and J. Bhaumik, “Comments On VLSI Implementation Of Reed-Solomon Encoder Algorithm For Communication Systems” in Radioelectronics and Communications Systems Journal (Springer), vol. 57, no. 7, pp:331-332,July,2014. (SCImago, IF-0.19). |
[10] | M. Suman, J. Samanta, D. Chowdhury and J. Bhaumik., “Relative Performance Analysis of Different CMOS Full Adder Circuits”, International Journal of Computer Applications, vol.114, no. 6, pp:8-14, March 2015., 973-93-80885-73-1. |
[11] | J. Samanta, J. Bhaumik and S. Barman, CA-based Area Optimized Three Bytes Error Detecting Codes, in Journal of Cellular Automata (Old City Publishing), (SCI Expanded, IF-0.698) vol.10, no.5-6, pp:409-423, Oct.-2015. ISSN: 1557-5969. |
[12] | J. Samanta, J. Bhaumik and S. Barman, MODIFIED KARATSUBA MULTIPLIER FOR ‘KEY EQUATION SOLVER’ IN RS CODE, in Radioelectronics and Communications Systems Journal (Springer), vol.58, no.10, pp:452-461, 2015. (SCImago, IF-0.19). |
[13] | J. Samanta, J. Bhaumik and Soma Barman, A transistor level implementation of Reed Solomon encoder in GF(28), in Journal of active and passive electronics devices (Old City Publishing), vol:11, no.2-3, pp:243-261, 2016. |
[14] | J. Samanta, J. Bhaumik and S. Barman, “FPGA based Area Efficient RS(23, 17) Codec”, Microsystems Technologies (Springer), (accepted) (SCIE). |
[1] | J Samanta and B P De,“Comprehensive analysis of delay in UDSM CMOS circuits”, Proceeding of, ICECCT’11, Villupuram, Tamil Nadu, India, IEEE explore, 978-1-4577-1894-6/11, Nov-2011, pp:29-32. (Paper Presented) |
[2] | J Samanta and B P De, “Delay analysis of UDSM CMOS VLSI circuits”, International Conference ICCSTD-2011, Kerala, Procedia Engineering, Volume 30, 2012, (Science Direct) March-2012, pp:135-142. (Paper Presented) |
[3] | A. K. Singh & J. Samanta, “Different Physical Effects in UDSM MOSFET for Delay & Power Estimation: A Review”, International Conference on Electrical, Electronics and Computer Science (SCEECS-2012), NIT Bhopal, ISBN-978-1-4673-1515-9/IEEE Explore, March-2012, pp:1-5. |
[4] | R. Dasgupta, D. Saha, J. Samanta, S. Chatterjee, C. K. Sarkar, “Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit”, VDAT 2012: pp:156-165 (Published by SpingerLink, Lecture Notes in Computer Science, July-2012, Volume 7373/2012, 156-165 |
[5] | A.K. Singh, J. Samanta & J. Bhaumik, “Modified I-V Model for Delay Analysis of UDSM CMOS Circuits”, International Conference on Communications, Devices and Intelligent Systems (CODIS), Jadavpur University, 978-1-4673-4700-6/12, IEEE Explore, Dec-2012, pp:369-372. (Paper Presented) |
[6] | J. Samanta, R. Sultana & J. Bhaumik, “FPGA Based Modified Karatsuba Multiplier” International Conf. on VLSI and Signal Processing (ICVSP14-IEEE Sponsored) at IIT KGP, Jan. 2014, pp:1-6.(Paper Presented). |
[7] | J. Samanta, J. Bhaumik & S. Barman, “Low Complexity 3-Symbol Error Detecting RS(23, 17) Code”. 3rd Int. Conf. on Computing, Communication and Sensor Network, (CCSN2014), PIET, Odshia, ISBN No.:81-85824-46-0, pp:30-37.(Paper Presented). |
[8] | J. Samanta, J. Bhaumik & S. Barman, “COMPACT RS(32, 28) ENCODER” Proc. of 1st Int. Conf. Intelligent Computing & Applications (ICICA 2014), NIT DGP, (Published by SpingerLink, Advances in Intelligent Systems and Computing Vol.-343, Feb 2015, pp. 89-95.) |
[1] | J. Samanta, A. K. Singh, “An improved MOSFET I-V model and its application in nano-CMOS circuits” Lap Lambert Academic Publishing, Germany, ISBN-978-3-659-44752-5, August-2013. Pages:72. |
[2] | J. Samanta, “UDSM CMOS Circuits: Delay and Power Models” Lap Lambert Academic Publishing, Germany, ISBN-978-3-659-52303-8, February-2014. Pages:97. |